
//--xuezhen--

`include "defines.v"

module SimTop(
  input         clock,
  input         reset,

  input  [63:0] io_logCtrl_log_begin,
  input  [63:0] io_logCtrl_log_end,
  input  [63:0] io_logCtrl_log_level,
  input         io_perfInfo_clean,
  input         io_perfInfo_dump,

  output        io_uart_out_valid,
  output [7:0]  io_uart_out_ch,
  output        io_uart_in_valid,
  input  [7:0]  io_uart_in_ch

  //to data mem
  //output wire [1:0]datasize,
  //output wire save_valid,
  //output wire [`REG_BUS]data,
  //output wire [`REG_BUS]addr
);

/*
// if_stage
wire [63 : 0] pc;
wire [31 : 0] inst;

// id_stage
// id_stage -> regfile
wire rs1_r_ena;
wire [4 : 0]rs1_r_addr;
wire rs2_r_ena;
wire [4 : 0]rs2_r_addr;
wire rd_w_ena;
wire [4 : 0]rd_w_addr;
// id_stage -> exe_stage
wire [4 : 0]inst_type;
wire [7 : 0]inst_opcode;
wire [`REG_BUS]op1;
wire [`REG_BUS]op2;

// regfile -> id_stage
wire [`REG_BUS] r_data1;
wire [`REG_BUS] r_data2;
// regfile -> difftest
wire [`REG_BUS] regs[0 : 31];

// exe_stage
// exe_stage -> other stage
wire [4 : 0]inst_type_o;
// exe_stage -> regfile
wire [`REG_BUS]rd_data;
*/

/*
if_stage If_stage(
  .clk                (clock),
  .rst                (reset),
  
  .pc                 (pc),
  .inst               (inst)
);*/

////////////////stall////////////////
reg stall;
always @(*) begin
  if ((rs1_r_ena == 1'b1) && (rs1_r_addr == exe_rd_w_addr) && (exe_rd_w_ena == 1'b1)) begin  
    stall = 1'b1;
  end
  else if ((rs1_r_ena == 1'b1) && (rs1_r_addr == mem_rd_w_addr) && (mem_rd_w_ena == 1'b1)) begin
    stall = 1'b1;
  end
  else if ((rs2_r_ena == 1'b1) && (rs2_r_addr == exe_rd_w_addr) && (exe_rd_w_ena == 1'b1)) begin  
    stall = 1'b1;
  end
  else if ((rs2_r_ena == 1'b1) && (rs2_r_addr == mem_rd_w_addr) && (mem_rd_w_ena == 1'b1)) begin
    stall = 1'b1;
  end
  else begin
    stall = 1'b0;
  end
end

////////////////id<-->reg////////////////
// id_stage -> regfile
wire rs1_r_ena;
wire [4 : 0]rs1_r_addr;
wire rs2_r_ena;
wire [4 : 0]rs2_r_addr;
// regfile -> id_stage
wire [`REG_BUS] r_data1;
wire [`REG_BUS] r_data2;


////////////////difftest<-->reg////////////////
// regfile -> difftest
wire [`REG_BUS] regs[0 : 31];



////////////////flush////////////////
wire flush;
wire [`REG_BUS]pc_dest;

////////////////PC_RESET////////////////
parameter PC_START_RESET = `PC_START - 4;


////////////////RAM_HELPER////////////////
wire [`REG_BUS]ctl_data_loaded;

wire ctl_ram_wr_en;
wire ctl_ram_rd_en;
wire [`REG_BUS]ctl_ram_wmask;
wire [`REG_BUS]ctl_ram_addr;
wire [`REG_BUS]ctl_ram_wr_data;


ram_helper_ctl ram_helper_ctl(
  .rst(reset),
  //from mem_stage 
  .mem_datasize(mem_datasize_2ram),
  .mem_addr(mem_addr_2ram),
  .mem_rd_en(mem_load_en_2ram),
  .mem_wr_en(mem_save_en_2ram),
  .mem_wr_data(mem_data_2ram),
  //to mem_stage
  .mem_rd_data(ctl_data_loaded),

  //to ram
  .ram_wr_en(ctl_ram_wr_en),
  .ram_rd_en(ctl_ram_rd_en),
  .ram_wmask(ctl_ram_wmask),
  .ram_addr(ctl_ram_addr),
  .ram_wr_data(ctl_ram_wr_data),

  //from ram
  .ram_rd_data(ram_rd_data)
);

wire [31:0]ram_inst;
wire [`REG_BUS]ram_rd_data;
ram_helper_2r ram_helper(
  .clk(clock),

  //from if_stage
  .inst_addr(if_inst_addr),
  .inst_ena(if_inst_ena),
  //reture to if_stage
  .inst(ram_inst),

  //from mem_stage
  .ram_wr_en(ctl_ram_wr_en),
  .ram_rd_en(ctl_ram_rd_en),
  .ram_wmask(ctl_ram_wmask),
  .ram_addr(ctl_ram_addr),
  .ram_wr_data(ctl_ram_wr_data),
  //reture to mem_stage
  .ram_rd_data(ram_rd_data)
);

////////////////if_stage////////////////
if_stage If_stage(
  .clk(clock),
  .rst(reset),

  .stall(stall),
  .flush(flush),
  .pc_dest(pc_dest),

  //from ram_helper
  .inst_i(ram_inst),
  
  //to ram_helper
  .inst_addr(if_inst_addr),
  .inst_ena(if_inst_ena),

  .pc(if_pc),
  .inst_o(if_inst)
);

//if_stage_out
wire [31:0] if_inst;
wire [`REG_BUS] if_pc;
wire [`REG_BUS] if_inst_addr;
wire if_inst_ena;

//if_stage -> id_stage
reg [31:0] if_id_inst;
reg [`REG_BUS] if_id_pc;
always @(posedge clock) begin
  if ((reset == 1'b1) || (flush == 1'b1)) begin
    if_id_inst <= 32'b0;
    //if_id_pc <= `ZERO_WORD;
    if_id_pc <= PC_START_RESET;
  end
  else begin
    if (stall == 1'b1) begin
      if_id_inst <= if_id_inst;
      if_id_pc <= if_id_pc;
    end
    else begin
      if_id_inst <= if_inst;
      if_id_pc <= if_pc;
    end
  end

end

////////////////id_stage////////////////
id_stage Id_stage(
  //.clk(clk),
  .rst(reset),
  .inst_i(if_id_inst),
  .pc_i(if_id_pc),

  //from reg
  .rs1_data(r_data1),
  .rs2_data(r_data2),
  
  //to reg
  .rs1_r_ena(rs1_r_ena),
  .rs1_r_addr(rs1_r_addr),
  .rs2_r_ena(rs2_r_ena),
  .rs2_r_addr(rs2_r_addr),
  //pass
  .rd_w_ena(id_rd_w_ena),
  .rd_w_addr(id_rd_w_addr),
  .inst_type(id_inst_type),
  .alu_opcode(id_alu_opcode),
  .alu_single_word(id_alu_single_word),
  .op1(id_op1),
  .op2(id_op2),
  .l_mem(id_l_mem),
  .s_mem(id_s_mem),
  .datasize(id_datasize),
  .unsigned_load(id_unsigned_load),
  .rs1_data_o(id_rs1_data),
  .rs2_data_o(id_rs2_data),
  .branch_type(id_branch_type),
  .jump_type(id_jump_type),
  .inst_o(id_inst),   //for difftest
  .pc_o(id_pc)
);


// id_stage_out
wire id_rd_w_ena;
wire [4 : 0]id_rd_w_addr;
wire [4 : 0]id_inst_type;
wire [7 : 0]id_alu_opcode;
wire id_alu_single_word;
wire [`REG_BUS]id_op1;
wire [`REG_BUS]id_op2;
wire id_l_mem;
wire id_s_mem;
wire [1:0]id_datasize;
wire id_unsigned_load;
wire [`REG_BUS]id_rs1_data;
wire [`REG_BUS]id_rs2_data;
wire [2:0]id_branch_type;
wire [1:0]id_jump_type;
wire [31:0] id_inst;
wire [`REG_BUS]id_pc;


// id_stage -> exe_stage
reg id_exe_rd_w_ena;
reg [4 : 0]id_exe_rd_w_addr;
reg [4 : 0]id_exe_inst_type;
reg [7 : 0]id_exe_alu_opcode;
reg id_exe_alu_single_word;
reg [`REG_BUS]id_exe_op1;
reg [`REG_BUS]id_exe_op2;
reg id_exe_l_mem;
reg id_exe_s_mem;
reg [1:0]id_exe_datasize;
reg id_exe_unsigned_load;
reg [`REG_BUS]id_exe_rs1_data;
reg [`REG_BUS]id_exe_rs2_data;
reg [2:0]id_exe_branch_type;
reg [1:0]id_exe_jump_type;
reg [31:0]id_exe_inst;
reg [`REG_BUS]id_exe_pc;
always @(posedge clock) begin
  if ((reset == 1'b1) || (stall == 1'b1) || (flush == 1'b1)) begin
    id_exe_rd_w_ena <= 1'b0;
    id_exe_rd_w_addr<=5'b00000;
    id_exe_inst_type<=5'b00000;
    id_exe_alu_opcode<=8'b00000000;
    id_exe_alu_single_word <= 1'b0;
    id_exe_op1<=`ZERO_WORD;
    id_exe_op2<=`ZERO_WORD;
    id_exe_l_mem<=1'b0;
    id_exe_s_mem<=1'b0;
    id_exe_datasize<=2'b00;
    id_exe_unsigned_load<=1'b0; 
    id_exe_rs1_data<=`ZERO_WORD;
    id_exe_rs2_data<=`ZERO_WORD;
    id_exe_branch_type<=3'b000;
    id_exe_jump_type<=2'b00;
    id_exe_inst<=32'b0;
    id_exe_pc<=PC_START_RESET;
  end
  else begin
    id_exe_rd_w_ena <= id_rd_w_ena;
    id_exe_rd_w_addr<=id_rd_w_addr;
    id_exe_inst_type<=id_inst_type;
    id_exe_alu_opcode<=id_alu_opcode;
    id_exe_alu_single_word<=id_alu_single_word;
    id_exe_op1<=id_op1;
    id_exe_op2<=id_op2;
    id_exe_l_mem<=id_l_mem;
    id_exe_s_mem<=id_s_mem;
    id_exe_datasize<=id_datasize;
    id_exe_unsigned_load<=id_unsigned_load; 
    id_exe_rs1_data<=id_rs1_data;
    id_exe_rs2_data<=id_rs2_data;
    id_exe_branch_type<=id_branch_type;
    id_exe_jump_type<=id_jump_type;
    id_exe_inst<=id_inst;
    id_exe_pc<=id_pc;
  end

end


////////////////exe_stage////////////////
exe_stage Exe_stage(
  .rst(reset),
  .rd_w_ena_i(id_exe_rd_w_ena),
  .rd_w_addr_i(id_exe_rd_w_addr),
  .inst_type_i(id_exe_inst_type),
  .alu_opcode(id_exe_alu_opcode),
  .alu_single_word(id_exe_alu_single_word),
  .op1(id_exe_op1),
  .op2(id_exe_op2),
  .l_mem_i(id_exe_l_mem),
  .s_mem_i(id_exe_s_mem),
  .datasize_i(id_exe_datasize),
  .unsigned_load_i(id_exe_unsigned_load),
  .rs1_data_i(id_exe_rs1_data),
  .rs2_data_i(id_exe_rs2_data),
  .branch_type(id_exe_branch_type),
  .jump_type(id_exe_jump_type),
  .inst_i(id_exe_inst),
  .pc_i(id_exe_pc),

  //result to out
  .alu_result_o(exe_alu_result),
  .flush(flush),    //flush to pc!
  .pc_dest(pc_dest),
  
  //pass
  .inst_type_o(exe_inst_type),
  .rd_w_ena_o(exe_rd_w_ena),
  .rd_w_addr_o(exe_rd_w_addr),
  .l_mem_o(exe_l_mem),
  .s_mem_o(exe_s_mem),
  .datasize_o(exe_datasize),
  .unsigned_load_o(exe_unsigned_load),
  .rs2_data_o(exe_rs2_data),
  .inst_o(exe_inst),
  .pc_o(exe_pc)
);

//exe_stage_out
wire exe_rd_w_ena;
wire [4 : 0]exe_rd_w_addr;
wire [4 : 0]exe_inst_type;
wire exe_l_mem;
wire exe_s_mem;
wire [1:0]exe_datasize;
wire exe_unsigned_load;
wire [`REG_BUS]exe_rs2_data;
wire [`REG_BUS]exe_alu_result;
wire [31:0] exe_inst;
wire [`REG_BUS]exe_pc;


//exe_stage -> mem_stage
reg exe_mem_rd_w_ena;
reg [4 : 0]exe_mem_rd_w_addr;
reg [4 : 0]exe_mem_inst_type;
reg exe_mem_l_mem;
reg exe_mem_s_mem;
reg [1:0]exe_mem_datasize;
reg exe_mem_unsigned_load;
reg [`REG_BUS]exe_mem_rs2_data;
reg [`REG_BUS]exe_mem_alu_result;
reg [31:0] exe_mem_inst;
reg [`REG_BUS]exe_mem_pc;
always @(posedge clock) begin
  if (reset == 1'b1) begin
    exe_mem_rd_w_ena<=1'b0;
    exe_mem_rd_w_addr<=5'b00000;
    exe_mem_inst_type<=5'b00000;
    exe_mem_l_mem<=1'b0;
    exe_mem_s_mem<=1'b0;
    exe_mem_datasize<=2'b00;
    exe_mem_unsigned_load<=1'b0;
    exe_mem_rs2_data<=`ZERO_WORD;
    exe_mem_alu_result<=`ZERO_WORD;
    exe_mem_inst<=32'b0;
    exe_mem_pc<=PC_START_RESET;
  end
  else begin
    exe_mem_rd_w_ena<=exe_rd_w_ena;
    exe_mem_rd_w_addr<=exe_rd_w_addr;
    exe_mem_inst_type<=exe_inst_type;
    exe_mem_l_mem<=exe_l_mem;
    exe_mem_s_mem<=exe_s_mem;
    exe_mem_datasize<=exe_datasize;
    exe_mem_unsigned_load<=exe_unsigned_load;
    exe_mem_rs2_data<=exe_rs2_data;
    exe_mem_alu_result<=exe_alu_result;
    exe_mem_inst<=exe_inst;
    exe_mem_pc<=exe_pc;
  end
  
end

////////////////mem_stage////////////////
mem_stage Mem_stage(
  //input
  .rst(reset),
  .inst_type_i(exe_mem_inst_type),
  .rd_w_ena_i(exe_mem_rd_w_ena),
  .rd_w_addr_i(exe_mem_rd_w_addr),
  .l_mem_i(exe_mem_l_mem),
  .s_mem_i(exe_mem_s_mem),
  .datasize_i(exe_mem_datasize),
  .unsigned_load_i(exe_mem_unsigned_load),
  .rs2_data_i(exe_mem_rs2_data),
  .alu_result_i(exe_mem_alu_result),
  .inst_i(exe_mem_inst),
  .pc_i(exe_mem_pc),


  //from ram
  .data_loaded(ctl_data_loaded),///////////////////////////////////////////////////not implemented yet///////////////////////////////////////////////////////////////
  .data_valid(1),///////////////////////////////////////////////////not implemented yet/////////////////////////////////////////////////////////////////

  //output
  //to ram
  .datasize_2ram(mem_datasize_2ram),
  .load_en_2ram(mem_load_en_2ram),
  .save_en_2ram(mem_save_en_2ram),
  .data_2ram(mem_data_2ram),
  .addr_2ram(mem_addr_2ram),

  //result
  .rd_w_data(mem_rd_w_data),
  //pass
  .inst_type_o(mem_inst_type),
  .rd_w_ena_o(mem_rd_w_ena),
  .rd_w_addr_o(mem_rd_w_addr),
  .inst_o(mem_inst),
  .pc_o(mem_pc)
);


////mem_stage_out
wire [`REG_BUS]mem_rd_w_data;
wire [4 : 0]mem_inst_type;
wire mem_rd_w_ena;
wire [4 : 0]mem_rd_w_addr;
wire [31:0]mem_inst;
wire [`REG_BUS]mem_pc;

wire [1:0]mem_datasize_2ram;
wire mem_load_en_2ram;
wire mem_save_en_2ram;
wire [`REG_BUS]mem_data_2ram;
wire [`REG_BUS]mem_addr_2ram;


////mem_stage -> wb_stage
reg [`REG_BUS]mem_wb_rd_w_data;
reg [4 : 0]mem_wb_inst_type;
reg mem_wb_rd_w_ena;
reg [4 : 0]mem_wb_rd_w_addr;
reg [31:0]mem_wb_inst;
reg [`REG_BUS]mem_wb_pc;

always @(posedge clock) begin
  if (reset == 1'b1) begin
    mem_wb_rd_w_ena <= 1'b0;
    mem_wb_rd_w_addr <= 5'b00000;
    mem_wb_inst_type <= 5'b00000;
    mem_wb_rd_w_data <= `ZERO_WORD;
    mem_wb_inst<=32'b0;
    mem_wb_pc<=PC_START_RESET;
  end
  else begin
    mem_wb_rd_w_ena <= mem_rd_w_ena;
    mem_wb_rd_w_addr <= mem_rd_w_addr;
    mem_wb_inst_type <= mem_inst_type;
    mem_wb_rd_w_data <= mem_rd_w_data; 
    mem_wb_inst<=mem_inst;
    mem_wb_pc<=mem_pc;  
  end

end

////////////////wb_stage////////////////
wb_stage Wb_stage(
  .rst(reset),
  .inst_type_i(mem_wb_inst_type),
  .rd_w_ena_i(mem_wb_rd_w_ena),
  .rd_w_addr_i(mem_wb_rd_w_addr),
  .rd_w_data_i(mem_wb_rd_w_data),
  .inst_i(mem_wb_inst),
  .pc_i(mem_wb_pc),
  
  //pass
  .inst_type_o(),
  .rd_w_ena_o(wb_rd_w_ena),
  .rd_w_addr_o(wb_rd_w_addr),
  .rd_w_data_o(wb_rd_w_data),
  .inst_o(wb_inst),
  .pc_o(wb_pc)
);

////wb_stage_out
wire wb_rd_w_ena;
wire [4 : 0]wb_rd_w_addr;
wire [4 : 0]wb_inst_type;
wire [`REG_BUS]wb_rd_w_data;
wire [31:0]wb_inst;
wire [`REG_BUS]wb_pc;

////////////////register////////////////
regfile Regfile(
  .clk(clock),
  .rst(reset),
  .w_addr(wb_rd_w_addr),
  .w_data(wb_rd_w_data),
  .w_ena(wb_rd_w_ena),
  
  .r_addr1(rs1_r_addr),
  .r_data1(r_data1),
  .r_ena1(rs1_r_ena),
  .r_addr2(rs2_r_addr),
  .r_data2(r_data2),
  .r_ena2(rs2_r_ena),

  .regs_o(regs)
);

/*
id_stage Id_stage(
  .rst                (reset),
  .inst               (inst),
  .rs1_data           (r_data1),
  .rs2_data           (r_data2),
  
  .rs1_r_ena          (rs1_r_ena),
  .rs1_r_addr         (rs1_r_addr),
  .rs2_r_ena          (rs2_r_ena),
  .rs2_r_addr         (rs2_r_addr),
  .rd_w_ena           (rd_w_ena),
  .rd_w_addr          (rd_w_addr),
  .inst_type          (inst_type),
  .inst_opcode        (inst_opcode),
  .op1                (op1),
  .op2                (op2)
);

exe_stage Exe_stage(
  .rst                (reset),
  .inst_type_i        (inst_type),
  .inst_opcode        (inst_opcode),
  .op1                (op1),
  .op2                (op2),
  
  .inst_type_o        (inst_type_o),
  .rd_data            (rd_data)
);

regfile Regfile(
  .clk                (clock),
  .rst                (reset),
  .w_addr             (rd_w_addr),
  .w_data             (rd_data),
  .w_ena              (rd_w_ena),
  
  .r_addr1            (rs1_r_addr),
  .r_data1            (r_data1),
  .r_ena1             (rs1_r_ena),
  .r_addr2            (rs2_r_addr),
  .r_data2            (r_data2),
  .r_ena2             (rs2_r_ena),

  .regs_o             (regs)    //this is forwarded regs
);
*/

// Difftest
reg cmt_wen;
reg [7:0] cmt_wdest;
reg [`REG_BUS] cmt_wdata;
reg [`REG_BUS] cmt_pc;
reg [31:0] cmt_inst;
reg cmt_valid;
reg trap;
reg [7:0] trap_code;
reg [63:0] cycleCnt;
reg [63:0] instrCnt;
reg [`REG_BUS] regs_diff [0 : 31];

wire inst_valid = (wb_pc != PC_START_RESET) && (wb_inst != 0);



always @(posedge clock) begin
  if (reset) begin
    {cmt_wen, cmt_wdest, cmt_wdata, cmt_pc, cmt_inst, cmt_valid, trap, trap_code, cycleCnt, instrCnt} <= 0;
  end
  else if (~trap) begin
    cmt_wen <= wb_rd_w_ena;
    cmt_wdest <= {3'd0, wb_rd_w_addr};
    cmt_wdata <= wb_rd_w_data;
    cmt_pc <= wb_pc;
    cmt_inst <= wb_inst;
    cmt_valid <= inst_valid;

		regs_diff <= regs;

    trap <= wb_inst[6:0] == 7'h6b;
    trap_code <= regs[10][7:0];
    cycleCnt <= cycleCnt + 1;
    if (inst_valid == 1'b1) begin
      instrCnt <= instrCnt + 1;
    end
    else begin
      instrCnt <= instrCnt + 0;
    end
    //instrCnt <= instrCnt + inst_valid;
  end
end

DifftestInstrCommit DifftestInstrCommit(
  .clock              (clock),
  .coreid             (0),
  .index              (0),
  .valid              (cmt_valid),
  .pc                 (cmt_pc),
  .instr              (cmt_inst),
  .skip               (0),
  .isRVC              (0),
  .scFailed           (0),
  .wen                (cmt_wen),
  .wdest              (cmt_wdest),
  .wdata              (cmt_wdata)
);

DifftestArchIntRegState DifftestArchIntRegState (
  .clock              (clock),
  .coreid             (0),
  .gpr_0              (regs_diff[0]),
  .gpr_1              (regs_diff[1]),
  .gpr_2              (regs_diff[2]),
  .gpr_3              (regs_diff[3]),
  .gpr_4              (regs_diff[4]),
  .gpr_5              (regs_diff[5]),
  .gpr_6              (regs_diff[6]),
  .gpr_7              (regs_diff[7]),
  .gpr_8              (regs_diff[8]),
  .gpr_9              (regs_diff[9]),
  .gpr_10             (regs_diff[10]),
  .gpr_11             (regs_diff[11]),
  .gpr_12             (regs_diff[12]),
  .gpr_13             (regs_diff[13]),
  .gpr_14             (regs_diff[14]),
  .gpr_15             (regs_diff[15]),
  .gpr_16             (regs_diff[16]),
  .gpr_17             (regs_diff[17]),
  .gpr_18             (regs_diff[18]),
  .gpr_19             (regs_diff[19]),
  .gpr_20             (regs_diff[20]),
  .gpr_21             (regs_diff[21]),
  .gpr_22             (regs_diff[22]),
  .gpr_23             (regs_diff[23]),
  .gpr_24             (regs_diff[24]),
  .gpr_25             (regs_diff[25]),
  .gpr_26             (regs_diff[26]),
  .gpr_27             (regs_diff[27]),
  .gpr_28             (regs_diff[28]),
  .gpr_29             (regs_diff[29]),
  .gpr_30             (regs_diff[30]),
  .gpr_31             (regs_diff[31])
);

DifftestTrapEvent DifftestTrapEvent(
  .clock              (clock),
  .coreid             (0),
  .valid              (trap),
  .code               (trap_code),
  .pc                 (cmt_pc),
  .cycleCnt           (cycleCnt),
  .instrCnt           (instrCnt)
);

DifftestCSRState DifftestCSRState(
  .clock              (clock),
  .coreid             (0),
  .priviledgeMode     (0),
  .mstatus            (0),
  .sstatus            (0),
  .mepc               (0),
  .sepc               (0),
  .mtval              (0),
  .stval              (0),
  .mtvec              (0),
  .stvec              (0),
  .mcause             (0),
  .scause             (0),
  .satp               (0),
  .mip                (0),
  .mie                (0),
  .mscratch           (0),
  .sscratch           (0),
  .mideleg            (0),
  .medeleg            (0)
);

DifftestArchFpRegState DifftestArchFpRegState(
  .clock              (clock),
  .coreid             (0),
  .fpr_0              (0),
  .fpr_1              (0),
  .fpr_2              (0),
  .fpr_3              (0),
  .fpr_4              (0),
  .fpr_5              (0),
  .fpr_6              (0),
  .fpr_7              (0),
  .fpr_8              (0),
  .fpr_9              (0),
  .fpr_10             (0),
  .fpr_11             (0),
  .fpr_12             (0),
  .fpr_13             (0),
  .fpr_14             (0),
  .fpr_15             (0),
  .fpr_16             (0),
  .fpr_17             (0),
  .fpr_18             (0),
  .fpr_19             (0),
  .fpr_20             (0),
  .fpr_21             (0),
  .fpr_22             (0),
  .fpr_23             (0),
  .fpr_24             (0),
  .fpr_25             (0),
  .fpr_26             (0),
  .fpr_27             (0),
  .fpr_28             (0),
  .fpr_29             (0),
  .fpr_30             (0),
  .fpr_31             (0)
);

endmodule